In this paper, a Multiple Coupled CMOS LC Quadrature Oscillator (MC-QO) in order to generate quadrature signals with a favorable PHASE NOISE and low power consumption is presented. In this work, the core of oscillator is coupled by the different passive and active coupling techniques in each stage. The active dynamic current-clipping technique is applied in the active coupling network, which can provides PHASE shift alone and results into the PHASE error and PHASE NOISE corrections of output signal. However, the passive coupling technique is also used in order to increase the corrections further. The passive coupling network consists of one RLC filter that besides the inherent reduction of NOISE, it provides compensating PHASE for reducing the resonator PHASE shift (RPS) in order to improve PHASE NOISE, which is proven by the analysis results. Using two coupling paths has a big contribution for increasing the coupling factor’ s value, which leads to the improvement of output’ s PHASE accuracy. Meanwhile, the passive coupling network does not dissipate additional power. Moreover, the applied tail current-shaping technique in the source of tail current causes the improvement of circuit’ s performance. To confirm the validity of the proposed quadrature oscillator’ s performance and the presented analysis, the MC-QO is simulated in TSMC 0. 18RF-CMOS technology at 3. 38 GHz fundamental frequency. The power consumption is 4. 6 mW from 1. 8 V power supply, the PHASE NOISE is-128. 2 (dBc/Hz) @ 1MHz and-138. 5 (dBc/Hz) @ 3 MHz offset frequencies with the quality factor (Q10. 8). Eventually, the excellent Figure of Merit (FOM) of-192. 25 (dBc/HZ) at 1 MHz offset frequency is achieved.

In this article, an X-band low PHASE NOISE dielectric resonator oscillator is investigated. For this purpose, a dielectric resonator as a frequency stabilization section at the almost center frequency of 12 GHz is designed. The active device is a packaged GaAs FET (an ATF-36077 pHEMT). Firstly, the ATF36077 microwave transistor has been biased. The substrate of this nonplanar oscillator is Rogers RT/Duroid 5880. Finally, the dielectric resonator oscillator has been introduced as a series feedback structure. This presented X-band dielectric resonator oscillator, operating at nearly 12 GHz, exhibits a PHASE NOISE of -71 dBc/Hz and -133 dBc/Hz at 1-kHz and 1-MHz frequency offset, respectively. Also, the output power level of nearly 7 dBm is achieved. The second and third harmonic power levels are more than 50 dB and 30 dB lower than the main harmonic power level.

This paper analyzes the PHASE NOISE of the single loop second-order frequency fractional-N synthesizer. The aim of this paper is the reduction of the output PHASE NOISE in the application of commercial and military subsystems as well as general local oscillators. The mathematical model of PLL based frequency synthesizer is analyzed to develop the minimum PHASE NOISE in the specific frequency range. An exact closed form relationship between bandwidth and output PHASE NOISE of the frequency synthesizer as well as the bandwidth-PHASE NOISE diagram is extracted by using this closed form relationship. From the analysis and simulation results, we observe that the system has minimum PHASE NOISE at a particular closed-loop bandwidth. To validate simulation results, the synthesizer is implemented on the low loss professional printed circuit board (PCB). Measurement setup is scheduled on spectrum analyzer 8562A in the span of 5MHz and 10MHz. These measurements show excellent results in output spectrum of the frequency synthesizer.

In this paper, a wideband Voltage-Controlled Oscillator (VCO) is presented that operates in 2.38GHz to 3.9GHz, representing 48.6% tuning range. This circuit has been aimed to the wireless and WiMAX networks. The proposed circuit has low KVCO (frequency variation per 1V) and hence, reduced spur, when used in a PHASE Locked Loop (PLL). This work also proposes a new method for optimization of capacitors values and transistors size in the capacitor bank. PHASE NOISE of the proposed circuit is -120.8 dBc/Hz at 3.9GHz center frequency, at 1MHz offset. The supply voltage is 1V and the power consumption is 4.1mW. The proposed circuit has been laid out using TSMC 0.18 um RF CMOS foundry design kit in CADENCE. The post-layout simulation results prove excellent performance of the proposed circuit.

In this paper, a method is provided for suppressing FM NOISE jammer signal with polynomial-PHASE in pulsed radar based on the discrete polynomial-PHASE transform. In the first step, DPT transform is used to estimate polynomial-PHASE coefficients and amplitude of jammer signal. In the second step, the jammer signal has been reconstructed using the estimated amplitude and PHASE of the jammer signal, Then, jamming is suppressed efficiently by subtracting the reconstructed jammer signal from the received signal. Mean square error and CRLB for polynomial coefficients and amplitude of jammer signal in presence of combined target signals and the receiver NOISE, are calculated theoretically for the case of linear frequency modulation, and then are compared with simulations. The detection performance of the proposed method is also shown.

In this paper, a Low NOISE Variable Gain Amplifier in Ka-frequency band is designed. This amplifier is digitally controlled by using switching transistors which change the gain with an accuracy of 5-bit resolution (32 steps). The output PHASE shift should be minimized within a Dynamic Range of 15 dB. The proposed structure includes a Low NOISE Amplifier and a Variable Gain Amplifier, with common-source structure and degenerative inductor. In the proposed structure, the main gain is achieved by LNA and the switching control bits are used in two stages of the VGA. Simulation illustrates a NOISE Figure of 5. 6 dB; bandwidth of 5. 34 GHz; S11, S22 less than-14 dB and Dynamic Range of 15 dB. By using a “ compensating inductor” in the source of switching transistors, the amount of PHASE shift was reduced, such that within the bandwidth of 1. 5 GHz it is less than 5 degrees. The post-layout simulation results, show a Dynamic Range of 18. 7 dB; a bandwidth of 2. 5 GHz; NOISE Figure of 6. 4 dB and return losses less than-10 dB. In addition to it, In EM analysis, all inductors and major RF paths are evaluated by “ Sonnet” software.

In this paper, a new method for extending and relaxing the NOISE-coupling (NC) technique is proposed to enhance the NOISE-shaping order without adding the number of integrators. The NOISE-shaping order of the introduced ∑∆ modulator whit applying a second-order NOISE-coupling technique is enhanced and its performance with optimizing the NOISE transfer function (NTF) zeros is improved. Also, by removing the analog adder at feedforward path and transferring it to a new feedback branch before the last integrator and adding second-order NC path can be decreased the input voltage swing to the quantizer. Thus, by improving the modulator resolution, power consumption can be reduced. Mathematical analyses and behavioural simulation results confirm the effectiveness of the new NC method. To examine its performance, a 2nd-order single loop ΣΔ modulator was designed. The new NOISE-coupling method is used to achieve the three-order NOISE shaping to increase the resolution with low complexity and low-power. The results show an outstanding improvement in signal-to-NOISE and distortion ratio (SNDR) compared to the conventional structure.

Introduction: Cochlear dead zones are defined as areas where the inner hair cells have been destroyed.Thresholds on the audiograms show the integrity of those parts of the ear that are tested. Care must be taken in interpretating audiograms. Thanks to the advances in understanding of cochlear functions, it is now possible to spot false responses that come from dead zones of the cochlea. Recently, cochlear dead regions have been detected via TEN (Threshold Equalizing NOISE) test in which ipsilateral broadband NOISE and threshold shifting are used.Materials and Methods: A review of the literature on the subject of dead zones published from 1993 to 2003 was performed using Pubmed, Ebsco, Science Direct, Google Scholar Thieme ProQuest databases and library sources. key word: were "cochlear dead zone", "traveling wave", "ten (threshold equalizing NOISE) test", "ipsilateral NOISE" and "real-ear measurement for hearing aids prescription".Conclusion: Hearing aids fitting process for patients with severe and sloping sensory neural hearing loss must be noted specially by amplifying active zone and avoiding amplification for dead region i.e., offering amplification to the transition frequencies that have better hearing than others, those among the fine regions and the dead zones. Dead zone detection may help in hearing aids fitting and fine tuning.

This article presents development and implementation of an integer N-type PHASE Locked Loop (PLL) module with two output frequencies of 1 and 4 GHz, each having a PHASE NOISE better than -110dBC/Hz@10k. The structure has 0 and 10dBm power levels at 1 and 4GHz output frequencies, respectively. Having two different outputs of 1 and 4 GHz at once, in addition to the 1.1 and 4.4GHz realized by the capability included in this design in which two additional outputs can be achieved by using the pins A0 to A4 and altering their status, makes this structure a good candidate for mass production. A two-step frequency division is employed in this work. The first step is realized using the frequency divider of order 4, and the second step is implemented inside the HMC440 IC, including a PFD and a counter. Compared to typical methods, this method presents a clean output by suppressing the spurs meant to be manifested using a single-step frequency division. This PLL is constructed in discrete and modular modes and employed in transceivers’ up-converter and down-converter blocks, Satellite communications, Cable TV links (CATV), Local Area Networks (LAN), Global Positioning Systems (GPS), test equipment, digital radios, military and commercial communications. For a specific example, the 4GHz frequency is used to up-converte or down-converte the received signals, and the 1-GHz frequency is usually used for the synthesizer module clock frequency. Advanced Design System (ADS) was used in the design, and OrCAD was used in the schematic design of the PLL module.